Flip chip is the name of a process in which a semiconductor Si chip is flipped over so that the connection pads face towards the substrate. Flip chip technology was first introduced by IBM in the solid logic technology hybrid modules. In the conventional flip chip bonding, ceramic carriers, typically alumina, have been used in combination with solder that has a melting temperature.
The need for high-density interconnects in cost-effective flip chip packaging is a motivation for using organic substrates. The core materials of organic substrates include glass fibers in an epoxy, a dielectric material, and a conductor material in the build-up layers of epoxy and copper. In contrast to ceramic substrates, organic substrates have lower capacitance and more resistive structures, which are conducive to high performance. Also, recently developed coreless organic substrates offer a reduction in both weight and height profile.
However, when organic substrates are used for the flip chip assembly, substrate bending and warpage can occur. This bending and warping must be addressed to guarantee high assembly yield. The bending and warpage can increase as the size of the organic substrate increases for high performance chips and components, and as the thickness of the organic substrate decreases, for example in coreless substrates.
For high performance flip chip applications, Cu-low k dielectric layers are widely used in the Back-end-of-line (BEOL) structure of Si chips to reduce capacitance in the interconnect layers, which now account for a majority of the capacitance. In recent applications of flip chips, ultra low k dielectric materials are used for lower capacitance. As the dielectric layers in the BEOL structure decrease from low k to ultra low k, the dielectric layers become more brittle because the porosity should be increased to reduce the capacitance. The ultimate goal of the dielectric layers is to provide an air gap because air has the lowest capacitance, but the stability of BEOL will decrease.
During the flip chip assembly process, the Si chip and the organic substrates experience a temperature cycle from room temperature to the melting temperature of solder materials, which make the interconnects between the Si chip and the organic substrate by melting and solidification of solder materials. The CTE mismatch between a Si chip (˜2.6 ppm/° C.) and an organic substrate (˜17 ppm/° C.) creates thermally-induced stress/strain in the flip-chip structure during the flip chip assembly process. The organic substrate expands and contracts more than the Si chip. This causes the organic substrate to bend after flip chip assembly because the Si chip and the substrate are connected by solder bumps and the Si chip is more rigid than the organic substrate.
The thermally-induced stress/strain in the flip-chip structure often results in a failure of the BEOL structure. This failure is becoming more common because low k dielectric layers are more fragile than solder joints. In addition, the increase in chip/substrate size and the use of coreless substrates apply greater stress on low k dielectrics.
Due to environmental concern with the use of lead-based (Pb-based) solders, the electronic manufacturing industry has hurried to replace Pb-based solders with Pb-free solders. The common Pb-free solders, such as Sn-0.7 wt % Cu, Sn-3.5 wt % Ag, and Sn—Ag—Cu, have higher melting points (about 217° C. to about 221° C.) than the melting point of eutectic SnPb solder (about 183° C.). Therefore, higher stress/strain develops in the BEOL structure of Si chips when a Pb-free solder is used in the flip chip assembly process.
By way of example, such thermally-induced stress can occur during a flip chip assembly process that uses a solder reflow process to connect the chip to a substrate. As shown in FIG. 1, a chip 100, such as a silicon (Si) chip, has a plurality of ball or bump limiting metallurgy contacts (BLM) 102 formed along a surface of the chip 100. The BLM 102 correspond to inputs/outputs (I/Os) of the chip 100. A solder bump 104 is placed on each BLM. The chip 100 is to be connected to a substrate 106, such as an organic substrate. The substrate 106 includes a plurality of pads 108. During a flip chip assembly process, chip 100 is placed onto the substrate 106 so that the bumps 104 align with the respective pads 108 of the substrate 106, as shown in FIG. 2. This portion of the assembly process is normally conducted at ambient room temperature.
The chip 100 is bonded to the substrate 106 by heating the flip chip assembly to a temperature that exceeds the melting temperature of the solder. During heating, the chip 100 and substrate 106 expand laterally, as shown in FIG. 3. The chip 100 and substrate 106 expand at different rates due to their different CTEs. Because a substrate 106 such as an organic substrate has a higher CTE than a silicon chip 100, the substrate 106 expands more than the chip 100 during heating.
After heating the flip chip assembly to a temperature that exceeds the melting temperature of the solder, the flip chip assembly is cooled. As the flip chip assembly cools, the chip 100 and substrate 106 contract, as shown in FIG. 4. Because the substrate 106 has a higher CTE than the silicon chip 100, the substrate 106 contracts more than the chip 100 during cooling of the flip chip assembly. As the temperature of the flip chip assembly drops below the melting point of the solder, the solder bumps 104 harden and secure the chip 100 to the substrate 106. During further cooling of the flip chip assembly, the substrate 106 continues to contract at a greater rate than the chip 100. The greater contraction of the substrate 106 relative to the chip 100 can produce shear, tensile, and compressive forces in the flip chip assembly that can produce stress and strain in the flip chip assembly. The stresses and strains can distort the assembly (also referred to as a flip chip package), for example by bending and/or warping the chip 100 and substrate 106, as shown in FIG. 4. Shearing forces can result at the junction of the bump 100 and BLM 102, as shown in FIG. 5, due to the greater shrinkage of the substrate 106 relative to the chip 100 during cooling. The stresses and strain can crack or delaminate the BEOL structure of the chip 100, or even cause cohesive failure between the layers of the chip 100. They can impair the electrical and mechanical connections between the flip chip 100 and the substrate 106, and degrade the performance of the flip chip assembly.
After the heating and cooling of the flip chip assembly is completed, the flip chip assembly may be cleansed of any flux that may be present and underfilled with an underfill material 110. The warping and bending that occur during the solder reflow process can permanently distort and deform the flip chip assembly, as shown in FIG. 6.
U.S. Pat. No. 7,015,066 B2 discloses a method for reducing thermal-mechanical stresses that occur in flip-chips during assembly by restraining the substrate in a fixture that engages the sides of the substrate. This arrangement does not effectively control the thermal-mechanical stresses that occur during chip assembly, particularly during a solder reflow process, and can increase the stress or strain that develops in the chip.
Accordingly, a method and apparatus are needed to manage the stresses and strain that occur during chip assembly and thereby reduce or prevent the bending or warping that can occurs during a chip assembly process, particularly one that includes a solder reflow or similar process.